FPG-120 · FPGA & Acceleration
HLS & HDL Coder Workflows
Generating hardware from higher-level descriptions, and knowing when the result is good enough.
Who this course is for
Engineers evaluating or adopting high-level synthesis — from C/C++ with Vitis HLS or from MATLAB/Simulink with HDL Coder — who need to know what the tools produce and when to trust it.
Prerequisites
Course outline
Day 1 — High-level synthesis mechanics
- What HLS compiles: functions to modules, loops to pipelines
- Pragmas: PIPELINE, UNROLL, DATAFLOW, ARRAY_PARTITION and their resource costs
- Initiation interval and throughput: reading the HLS schedule
- Interface synthesis: how your arguments become AXI-Lite and AXI-Stream ports
- Arbitrary-precision types (ap_int, ap_fixed) and what they save
Day 2 — MATLAB and Simulink to HDL
- The HDL Coder workflow: model to RTL with the workflow advisor
- Fixed-Point Designer: word-length proposals and what to override
- HDL optimizations in Simulink: pipelining, resource sharing, streaming
- HDL cosimulation and FPGA-in-the-loop verification
- Comparing the generated interfaces with what a hand design would expose
Day 3 — Verification and judgment
- Verifying generated RTL against the golden model: bit-true vs cycle-approximate
- C/RTL cosimulation and its blind spots
- Numerical validation: quantisation error budgets through the generated chain
- Where hand-written RTL still wins: latency-critical loops, exotic interfaces, tight resources
- A decision framework: HLS for iteration speed, RTL for control — argued with evidence
Hands-on labs
Labs follow the academy model — 35% principles, 20% guided investigation, 45% engineering studio. Every claim you make in a lab is backed by a trace, a counter or a measurement you captured yourself. How we teach
- Lab: Synthesize a C kernel with Vitis HLS; sweep PIPELINE and UNROLL pragmas and graph initiation interval against resource use
- Lab: Convert a floating-point reference to ap_fixed, set word lengths from a stated error budget, and validate against golden vectors
- Lab: Generate HDL from a Simulink model with HDL Coder and run HDL cosimulation against the model
- Lab: Read the RTL both flows generated; identify the structures the tools produced and what you would have written differently
- Lab: Take one kernel through both HLS and hand-written RTL and compare latency, resources and effort honestly
Capstone project
Take one numerical kernel (a filter chain) from floating-point reference to a synthesized accelerator twice — once via HLS or HDL Coder, once as hand-written RTL informed by what you learned reading the generated code — and deliver the comparison the tool marketing will not: verified numerical error against the golden model, initiation interval and latency, resource and timing reports, and a defensible verdict on which flow fits which part of your own roadmap.
What you leave with
- A working Vitis HLS flow: pragmas, scheduling reports, interface synthesis
- HDL Coder literacy: from Simulink model to verified RTL
- Fixed-point conversion discipline driven by error budgets, not guesswork
- The habit of reading generated RTL before trusting it
- An evidence-based HLS-vs-RTL decision framework you can reuse
How it runs
Every course follows the same model: 35% principles, 20% guided investigation, 45% engineering studio. You leave with working code, raw measurements and an evidence-based report — not a certificate of attendance. Read the methodology or see a full sample lesson.
Material is adapted to your kernel version, hardware and workload before a private delivery. For public cohorts, the environment is provided and configured.
Questions
Who is this course for?
Engineers evaluating or adopting high-level synthesis — from C/C++ with Vitis HLS or from MATLAB/Simulink with HDL Coder — who need to know what the tools produce and when to trust it. It sits at practitioner level within the FPGA & Acceleration track.
What do I need to know already?
Specific prerequisites for this course: C/C++ proficiency; MATLAB/Simulink for the HDL Coder sessions; FPG-101-level RTL reading ability — you will be reading generated RTL; Basic DSP concepts helpful for the examples. We confirm levels before the cohort starts and adapt if a group is stronger or weaker than expected.
Can this run privately for my team?
Yes. Any course runs on-site at your offices anywhere, or live online for a distributed team, with labs adapted to your hardware and codebase.
What is the difference between in-person and online?
In person is 3 full days with hardware on your desk, capped at 14. Online is 6 half-day sessions across about two weeks so you can keep working, capped at 20, with remote lab access.
Do you invoice companies?
Yes. Purchase orders are accepted and invoicing is available in USD, EUR, GBP, SAR and CAD.
Upcoming dates
| Dates | Where | Seats | Early bird | Regular | |
|---|---|---|---|---|---|
| 15 Nov – 17 Nov 20263 full days | RiyadhIn person · KAFD Conference Centre | 6 of 14 | SAR 7,090until 16 Oct | ||
| 15 Nov – 17 Nov 20263 full days | Kuwait CityIn person · Al Hamra Tower | 11 of 14 | KWD 580until 16 Oct | ||
| 22 Nov – 24 Nov 20263 full days | MuscatIn person · Knowledge Oasis Muscat | 6 of 14 | OMR 730until 23 Oct | ||
| 29 Nov – 6 Dec 20266 half-days | Gulf bandLive online · 09:00–13:00 GMT+3 | 18 of 20 | US$1,350until 30 Oct | ||
| 30 Nov – 2 Dec 20263 full days | OttawaIn person · Kanata North Tech Park | 11 of 14 | CAD 2,570until 31 Oct | ||
| 30 Nov – 2 Dec 20263 full days | TorontoIn person · MaRS Discovery District | 6 of 14 | CAD 2,570until 31 Oct | ||
| 30 Nov – 7 Dec 20266 half-days | Europe bandLive online · 09:00–13:00 CET | 7 of 20 | US$1,350until 31 Oct | ||
| 7 Dec – 9 Dec 20263 full days | LondonIn person · Shoreditch Works | 11 of 14 | GBP 1,480until 7 Nov | ||
| 7 Dec – 14 Dec 20266 half-days | Americas bandLive online · 13:00–17:00 ET | 12 of 20 | US$1,350until 7 Nov | ||
| 14 Dec – 16 Dec 20263 full days | BerlinIn person · Factory Görlitzer Park | 6 of 14 | EUR 1,740until 14 Nov |
Dates shown for the next few months. If nothing fits, tell us where and when — cohorts are added on demand, and private delivery can be scheduled any week.
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