ARC-110 · Processor Architecture
SIMD & Vector Processing
Data-parallel execution on CPUs: AVX-512, NEON and SVE, and how to get the compiler to actually use them.
Who this course is for
Software engineers writing compute-heavy code who suspect the compiler is leaving vector performance on the table and want to prove it either way.
Prerequisites
Course outline
Day 1 — Vector hardware and instruction sets
- Vector register files and lane semantics
- AVX-512 on x86-64; NEON and SVE on Arm
- SVE's vector-length-agnostic model and predication
- Auto-vectorisation: what the compiler needs to see and how to check with -fopt-info-vec / -Rpass
- Alignment, aliasing and restrict: the three things that block vectorisation
Day 2 — When auto-vectorisation is not enough
- Intrinsics and inline assembly as controlled fallbacks
- Horizontal reductions, shuffles and masked operations
- Frequency effects and licence-based downclocking on wide vectors
- When vectorisation makes things slower
- Verifying claims with perf and cycle-accurate microbenchmarks
Hands-on labs
Labs follow the academy model — 35% principles, 20% guided investigation, 45% engineering studio. Every claim you make in a lab is backed by a trace, a counter or a measurement you captured yourself. How we teach
- Lab: auto-vectorise a hot loop with GCC/Clang, read the vectoriser report, and verify the speedup with perf stat
- Lab: rewrite a loop the compiler refuses to vectorise using AVX-512 or NEON intrinsics and compare against the scalar baseline
- Lab: measure the frequency behaviour of a heavy AVX-512 workload with perf and turbostat and quantify when narrow code wins
- Lab: run a fixed-width kernel next to an SVE-style predicated version under QEMU and document what the vector-length-agnostic model changes
Capstone project
Take a real numeric kernel from scalar to measured vectorised form: first through compiler auto-vectorisation with the vectoriser report as evidence, then, where the compiler falls short, with intrinsics. Deliver a comparison table of cycles, instructions and IPC for the scalar, auto-vectorised and hand-written versions, plus a defensible statement of when each approach is appropriate.
What you leave with
- The ability to make the compiler vectorise and to prove it did
- Working intrinsics skills on AVX-512 and NEON
- A quantitative answer to whether vectorising a given loop is worth it
- Familiarity with SVE's vector-length-agnostic model using QEMU
How it runs
Every course follows the same model: 35% principles, 20% guided investigation, 45% engineering studio. You leave with working code, raw measurements and an evidence-based report — not a certificate of attendance. Read the methodology or see a full sample lesson.
Material is adapted to your kernel version, hardware and workload before a private delivery. For public cohorts, the environment is provided and configured.
Questions
Who is this course for?
Software engineers writing compute-heavy code who suspect the compiler is leaving vector performance on the table and want to prove it either way. It sits at practitioner level within the Processor Architecture track.
What do I need to know already?
Specific prerequisites for this course: Solid C programming; Comfort reading compiler assembly output; ARC-101 or equivalent pipeline knowledge. We confirm levels before the cohort starts and adapt if a group is stronger or weaker than expected.
Can this run privately for my team?
Yes. Any course runs on-site at your offices anywhere, or live online for a distributed team, with labs adapted to your hardware and codebase.
What is the difference between in-person and online?
In person is 2 full days with hardware on your desk, capped at 14. Online is 4 half-day sessions across about two weeks so you can keep working, capped at 20, with remote lab access.
Do you invoice companies?
Yes. Purchase orders are accepted and invoicing is available in USD, EUR, GBP, SAR and CAD.
Upcoming dates
| Dates | Where | Seats | Early bird | Regular | |
|---|---|---|---|---|---|
| 15 Nov – 16 Nov 20262 full days | RiyadhIn person · KAFD Conference Centre | 10 of 14 | SAR 4,720until 16 Oct | ||
| 22 Nov – 23 Nov 20262 full days | Kuwait CityIn person · Al Hamra Tower | 5 of 14 | KWD 390until 23 Oct | ||
| 29 Nov – 30 Nov 20262 full days | MuscatIn person · Knowledge Oasis Muscat | 10 of 14 | OMR 490until 30 Oct | ||
| 29 Nov – 2 Dec 20264 half-days | Gulf bandLive online · 09:00–13:00 GMT+3 | 8 of 20 | US$900until 30 Oct | ||
| 30 Nov – 1 Dec 20262 full days | OttawaIn person · Kanata North Tech Park | 5 of 14 | CAD 1,710until 31 Oct | ||
| 7 Dec – 8 Dec 20262 full days | TorontoIn person · MaRS Discovery District | 10 of 14 | CAD 1,710until 7 Nov | ||
| 7 Dec – 10 Dec 20264 half-days | Europe bandLive online · 09:00–13:00 CET | 13 of 20 | US$900until 7 Nov | ||
| 14 Dec – 15 Dec 20262 full days | LondonIn person · Shoreditch Works | 5 of 14 | GBP 980until 14 Nov | ||
| 14 Dec – 17 Dec 20264 half-days | Americas bandLive online · 13:00–17:00 ET | 18 of 20 | US$900until 14 Nov | ||
| 21 Dec – 22 Dec 20262 full days | BerlinIn person · Factory Görlitzer Park | 10 of 14 | EUR 1,160until 21 Nov |
Dates shown for the next few months. If nothing fits, tell us where and when — cohorts are added on demand, and private delivery can be scheduled any week.
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