ARC-210 · Processor Architecture · Practitioner

PCIe & System Interconnects — full syllabus

The fabric between CPU, memory and devices: PCIe generations, topology, and the bandwidth you actually get.

Duration3 full days in person · 6 half-days online
Cohortmax 14 in person · 20 online
Pricefrom SAR 7,880 in person · local pricing per city
Delivery35% principles · 20% guided investigation · 45% engineering studio

Who this course is for

Driver, platform and hardware-adjacent engineers who need to understand the fabric between CPU, memory and devices well enough to debug it.

Prerequisites

Course outline

Day 1 — The link and the topology

  • PCIe Gen3/4/5: lanes, encoding (128b/130b) and realistic per-direction throughput
  • Root complexes, switches, bridges and enumeration
  • Bus/device/function addressing
  • Walking the topology with lspci -tv and /sys/bus/pci
  • The lane math: predicting achievable bandwidth before you measure it

Day 2 — Configuration space and the software view

  • Configuration space layout and the ECAM access mechanism
  • BARs and MMIO: how a device gets its address windows
  • Capabilities lists and how to walk them
  • MSI/MSI-X interrupt delivery
  • Reading lspci -vvv and setpci output; what the kernel does during enumeration

Day 3 — Transfers, peers and performance

  • DMA and how devices actually move memory
  • TLPs, flow control and ordering rules at a working level
  • Peer-to-peer transfers between devices
  • The IOMMU's place in the path
  • Diagnosing link degradation: negotiated versus capable speed and width

Hands-on labs

  1. Lab: walk an unfamiliar machine's PCIe topology with lspci -tv and sysfs and produce a labelled fabric diagram
  2. Lab: decode a device's configuration space with lspci -xxxx and setpci: BARs, capabilities and MSI-X tables
  3. Lab: check negotiated link speed and width against capability with lspci -vv and explain any downgrade found
  4. Lab: measure device-to-host bandwidth on a real device (NVMe or NIC) and compare it against the lane math
  5. Lab: inspect IOMMU groups and DMA-remapping state under /sys/kernel/iommu_groups on a suitably configured system

Capstone project

Produce a platform interconnect dossier for a supplied (or your own) server: a full PCIe topology map, a per-device negotiated-versus-capable link audit, a BAR and interrupt-mechanism inventory, and a measured bandwidth check on one device — closing with the topology facts most likely to matter for performance, each tied to the command output that established it.

What you leave with

Upcoming dates

DatesWhereSeatsEarly birdRegular
25 Oct – 27 Oct 20263 full days RiyadhIn person · KAFD Conference Centre 11 of 14 —SAR 7,880
25 Oct – 27 Oct 20263 full days Kuwait CityIn person · Al Hamra Tower 6 of 14 —KWD 650
1 Nov – 3 Nov 20263 full days MuscatIn person · Knowledge Oasis Muscat 11 of 14 —OMR 810
8 Nov – 15 Nov 20266 half-days Gulf bandLive online · 09:00–13:00 GMT+3 9 of 20 US$1,350until 9 OctUS$1,500
9 Nov – 11 Nov 20263 full days OttawaIn person · Kanata North Tech Park 6 of 14 CAD 2,570until 10 OctCAD 2,860
9 Nov – 11 Nov 20263 full days TorontoIn person · MaRS Discovery District 11 of 14 CAD 2,570until 10 OctCAD 2,860
9 Nov – 16 Nov 20266 half-days Europe bandLive online · 09:00–13:00 CET 14 of 20 US$1,350until 10 OctUS$1,500
16 Nov – 18 Nov 20263 full days LondonIn person · Shoreditch Works 6 of 14 GBP 1,480until 17 OctGBP 1,640
16 Nov – 23 Nov 20266 half-days Americas bandLive online · 13:00–17:00 ET 3 of 20 US$1,350until 17 OctUS$1,500
23 Nov – 25 Nov 20263 full days BerlinIn person · Factory Görlitzer Park 11 of 14 EUR 1,740until 24 OctEUR 1,930

Book a seat, or bring this course to your team

Seats can be reserved online; private delivery runs on-site or live online, adapted to your stack.

Course page & booking

Questions about fit or prerequisites? Email hello@kernelsystems.academy. To save this syllabus, print this page to PDF from your browser.