DRV-220 · Device Drivers
PCI & PCIe Drivers
Enumeration, BARs, MSI-X and DMA for PCIe devices, which is where most accelerator drivers live.
Who this course is for
Driver engineers working on PCIe devices — accelerators, FPGAs, NICs — who need enumeration, MSI-X and DMA set up correctly, and recovery paths that work when the device misbehaves.
Prerequisites
Course outline
Day 1 — Discovery and probe
- Enumeration, BDF addressing and the PCIe topology
- Configuration space, capabilities and extended capabilities
- pci_driver, pci_device_id and the probe sequence
- pci_enable_device, region claiming and BAR sizing
- Reading lspci -vv and setpci output precisely
Day 2 — MMIO done correctly
- Mapping BARs with pcim_iomap_regions and pci_iomap
- ioread32/iowrite32 and their ordering guarantees
- Write posting, flush reads and the bugs they hide
- Memory barriers for device access: wmb/rmb and mmiowb
- 64-bit BARs and the pitfalls of split register access
Day 3 — Interrupts and DMA setup
- Legacy INTx vs MSI vs MSI-X and what each costs
- pci_alloc_irq_vectors and per-vector affinity
- DMA addressing: dma_set_mask_and_coherent and why 64-bit matters
- Coherent allocations with dma_alloc_coherent
- Building a descriptor ring the device can walk
Day 4 — Robustness and advanced features
- AER: the error handler callbacks and what recovery means
- Function-level reset and secondary bus reset
- SR-IOV: enabling VFs and the PF/VF driver split
- Safe unload under traffic: quiesce, mask, drain, free
- Hotplug and surprise-removal behaviour
Hands-on labs
Labs follow the academy model — 35% principles, 20% guided investigation, 45% engineering studio. Every claim you make in a lab is backed by a trace, a counter or a measurement you captured yourself. How we teach
- Lab: Walk a PCIe device's config space with lspci -xxxx and match every capability to the driver path that consumes it
- Lab: Write a probe that claims BARs, maps MMIO and reads a device ID register from real or emulated hardware
- Lab: Allocate MSI-X vectors, steer their affinity and prove the spread in /proc/interrupts
- Lab: Implement a coherent DMA ring exchange and verify data lands intact in both directions
- Lab: Exercise the recovery path: trigger an FLR (or observe an AER report) and walk error_detected through slot_resume
Capstone project
Deliver a PCI driver skeleton for an emulated or FPGA device: probe with capability discovery, BAR mapping, MSI-X with steered affinity, a coherent DMA ring, and the AER/FLR recovery callbacks — with an evidence pack of annotated lspci output, /proc/interrupts proof of vector spread, a DMA correctness test and a recovery log from a forced reset.
What you leave with
- A complete PCIe driver skeleton you understand end to end
- Correct MMIO access and ordering habits
- MSI-X allocation and affinity steering proven with interrupts data
- Coherent DMA setup for device communication
- Error-recovery structure (AER/FLR) that works before you need it
How it runs
Every course follows the same model: 35% principles, 20% guided investigation, 45% engineering studio. You leave with working code, raw measurements and an evidence-based report — not a certificate of attendance. Read the methodology or see a full sample lesson.
Material is adapted to your kernel version, hardware and workload before a private delivery. For public cohorts, the environment is provided and configured.
Questions
Who is this course for?
Driver engineers working on PCIe devices — accelerators, FPGAs, NICs — who need enumeration, MSI-X and DMA set up correctly, and recovery paths that work when the device misbehaves. It sits at advanced level within the Device Drivers track.
What do I need to know already?
Specific prerequisites for this course: DRV-110 level device-model knowledge; C and kernel module build experience; ARC-210 (PCIe interconnects) or equivalent platform knowledge recommended. We confirm levels before the cohort starts and adapt if a group is stronger or weaker than expected.
Can this run privately for my team?
Yes. Any course runs on-site at your offices anywhere, or live online for a distributed team, with labs adapted to your hardware and codebase.
What is the difference between in-person and online?
In person is 4 full days with hardware on your desk, capped at 14. Online is 8 half-day sessions across about two weeks so you can keep working, capped at 20, with remote lab access.
Do you invoice companies?
Yes. Purchase orders are accepted and invoicing is available in USD, EUR, GBP, SAR and CAD.
Upcoming dates
| Dates | Where | Seats | Early bird | Regular | |
|---|---|---|---|---|---|
| 1 Nov – 4 Nov 20264 full days | RiyadhIn person · KAFD Conference Centre | 8 of 14 | — | SAR 12,000 | |
| 8 Nov – 11 Nov 20264 full days | Kuwait CityIn person · Al Hamra Tower | 3 of 14 | KWD 890until 9 Oct | ||
| 8 Nov – 11 Nov 20264 full days | MuscatIn person · Knowledge Oasis Muscat | 8 of 14 | OMR 1,110until 9 Oct | ||
| 15 Nov – 24 Nov 20268 half-days | Gulf bandLive online · 09:00–13:00 GMT+3 | 14 of 20 | US$2,070until 16 Oct | ||
| 16 Nov – 19 Nov 20264 full days | OttawaIn person · Kanata North Tech Park | 3 of 14 | CAD 3,920until 17 Oct | ||
| 16 Nov – 25 Nov 20268 half-days | Europe bandLive online · 09:00–13:00 CET | 3 of 20 | US$2,070until 17 Oct | ||
| 23 Nov – 26 Nov 20264 full days | TorontoIn person · MaRS Discovery District | 8 of 14 | CAD 3,920until 24 Oct | ||
| 23 Nov – 26 Nov 20264 full days | LondonIn person · Shoreditch Works | 3 of 14 | GBP 2,250until 24 Oct | ||
| 23 Nov – 2 Dec 20268 half-days | Americas bandLive online · 13:00–17:00 ET | 8 of 20 | US$2,070until 24 Oct | ||
| 30 Nov – 3 Dec 20264 full days | BerlinIn person · Factory Görlitzer Park | 8 of 14 | EUR 2,650until 31 Oct |
Dates shown for the next few months. If nothing fits, tell us where and when — cohorts are added on demand, and private delivery can be scheduled any week.
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