FPG-120 · FPGA & Acceleration · Practitioner
HLS & HDL Coder Workflows — full syllabus
Generating hardware from higher-level descriptions, and knowing when the result is good enough.
Who this course is for
Engineers evaluating or adopting high-level synthesis — from C/C++ with Vitis HLS or from MATLAB/Simulink with HDL Coder — who need to know what the tools produce and when to trust it.
Prerequisites
- C/C++ proficiency; MATLAB/Simulink for the HDL Coder sessions
- FPG-101-level RTL reading ability — you will be reading generated RTL
- Basic DSP concepts helpful for the examples
Course outline
Day 1 — High-level synthesis mechanics
- What HLS compiles: functions to modules, loops to pipelines
- Pragmas: PIPELINE, UNROLL, DATAFLOW, ARRAY_PARTITION and their resource costs
- Initiation interval and throughput: reading the HLS schedule
- Interface synthesis: how your arguments become AXI-Lite and AXI-Stream ports
- Arbitrary-precision types (ap_int, ap_fixed) and what they save
Day 2 — MATLAB and Simulink to HDL
- The HDL Coder workflow: model to RTL with the workflow advisor
- Fixed-Point Designer: word-length proposals and what to override
- HDL optimizations in Simulink: pipelining, resource sharing, streaming
- HDL cosimulation and FPGA-in-the-loop verification
- Comparing the generated interfaces with what a hand design would expose
Day 3 — Verification and judgment
- Verifying generated RTL against the golden model: bit-true vs cycle-approximate
- C/RTL cosimulation and its blind spots
- Numerical validation: quantisation error budgets through the generated chain
- Where hand-written RTL still wins: latency-critical loops, exotic interfaces, tight resources
- A decision framework: HLS for iteration speed, RTL for control — argued with evidence
Hands-on labs
- Lab: Synthesize a C kernel with Vitis HLS; sweep PIPELINE and UNROLL pragmas and graph initiation interval against resource use
- Lab: Convert a floating-point reference to ap_fixed, set word lengths from a stated error budget, and validate against golden vectors
- Lab: Generate HDL from a Simulink model with HDL Coder and run HDL cosimulation against the model
- Lab: Read the RTL both flows generated; identify the structures the tools produced and what you would have written differently
- Lab: Take one kernel through both HLS and hand-written RTL and compare latency, resources and effort honestly
Capstone project
Take one numerical kernel (a filter chain) from floating-point reference to a synthesized accelerator twice — once via HLS or HDL Coder, once as hand-written RTL informed by what you learned reading the generated code — and deliver the comparison the tool marketing will not: verified numerical error against the golden model, initiation interval and latency, resource and timing reports, and a defensible verdict on which flow fits which part of your own roadmap.
What you leave with
- A working Vitis HLS flow: pragmas, scheduling reports, interface synthesis
- HDL Coder literacy: from Simulink model to verified RTL
- Fixed-point conversion discipline driven by error budgets, not guesswork
- The habit of reading generated RTL before trusting it
- An evidence-based HLS-vs-RTL decision framework you can reuse
Upcoming dates
| Dates | Where | Seats | Early bird | Regular | |
|---|---|---|---|---|---|
| 15 Nov – 17 Nov 20263 full days | RiyadhIn person · KAFD Conference Centre | 6 of 14 | SAR 7,090until 16 Oct | ||
| 15 Nov – 17 Nov 20263 full days | Kuwait CityIn person · Al Hamra Tower | 11 of 14 | KWD 580until 16 Oct | ||
| 22 Nov – 24 Nov 20263 full days | MuscatIn person · Knowledge Oasis Muscat | 6 of 14 | OMR 730until 23 Oct | ||
| 29 Nov – 6 Dec 20266 half-days | Gulf bandLive online · 09:00–13:00 GMT+3 | 18 of 20 | US$1,350until 30 Oct | ||
| 30 Nov – 2 Dec 20263 full days | OttawaIn person · Kanata North Tech Park | 11 of 14 | CAD 2,570until 31 Oct | ||
| 30 Nov – 2 Dec 20263 full days | TorontoIn person · MaRS Discovery District | 6 of 14 | CAD 2,570until 31 Oct | ||
| 30 Nov – 7 Dec 20266 half-days | Europe bandLive online · 09:00–13:00 CET | 7 of 20 | US$1,350until 31 Oct | ||
| 7 Dec – 9 Dec 20263 full days | LondonIn person · Shoreditch Works | 11 of 14 | GBP 1,480until 7 Nov | ||
| 7 Dec – 14 Dec 20266 half-days | Americas bandLive online · 13:00–17:00 ET | 12 of 20 | US$1,350until 7 Nov | ||
| 14 Dec – 16 Dec 20263 full days | BerlinIn person · Factory Görlitzer Park | 6 of 14 | EUR 1,740until 14 Nov |
Book a seat, or bring this course to your team
Seats can be reserved online; private delivery runs on-site or live online, adapted to your stack.
Questions about fit or prerequisites? Email hello@kernelsystems.academy. To save this syllabus, print this page to PDF from your browser.