RISC-V Systems Programming

RISC-V privileged architecture for engineers arriving from x86 or Arm, including the state of the software ecosystem.

Advanced 3 days in person6 half-days online Max 14 in person

Who this course is for

Engineers evaluating or porting to RISC-V who need the privileged architecture and the real state of the ecosystem, not the brochure version.

Prerequisites

C and assembly reading abilityExposure to another ISA's privileged architecture (x86-64 or Arm64)Linux systems programming experience

Course outline

Day 1 — The ISA and its modularity

Base ISA, standard extensions and profiles
What 'RISC-V' on a datasheet does and does not promise
Machine, supervisor and user modes
CSRs and the trap model
Reading the privileged specification without drowning

Day 2 — Virtual memory and platform services

Sv39/Sv48 paging and the page-table formats
The SBI interface and what still lives in machine mode
PLIC and CLINT interrupt handling
The boot flow from OpenSBI to the kernel
Walking every piece in QEMU virt

Day 3 — The ecosystem as it is

Toolchain, emulation and hardware availability today
Extensions of systems interest, including the vector extension
Portability pitfalls arriving from x86 or Arm
Performance expectations and how to measure rather than assume
An honest read of what is ready and what is not

Hands-on labs

Labs follow the academy model — 35% principles, 20% guided investigation, 45% engineering studio. Every claim you make in a lab is backed by a trace, a counter or a measurement you captured yourself. How we teach

Lab: boot a RISC-V Linux kernel under QEMU virt, trace the OpenSBI handoff, and enumerate extensions from the device tree and CSRs
Lab: walk an Sv39 page table for a live process and decode the PTE bits by hand
Lab: trigger and decode traps through the SBI call path, reading scause, stval and sepc
Lab: cross-compile a workload with the RISC-V toolchain, run it under QEMU, and compare measured behaviour against an x86-64 baseline

Capstone project

Assemble a bring-up notebook for a RISC-V platform in QEMU: a boot-flow trace from firmware to kernel, a CSR and extension inventory, a hand-decoded page-table walk, and an SBI/PLIC interrupt exercise — closing with an honest assessment of what porting a stated piece of software to this platform would actually involve.

What you leave with

A precise picture of RISC-V privilege modes, CSRs and paging
Hands-on SBI, PLIC and CLINT experience under QEMU
A cross-compilation and emulation workflow that works today
An evidence-based view of the ecosystem's current limits

How it runs

Every course follows the same model: 35% principles, 20% guided investigation, 45% engineering studio. You leave with working code, raw measurements and an evidence-based report — not a certificate of attendance. Read the methodology or see a full sample lesson.

Material is adapted to your kernel version, hardware and workload before a private delivery. For public cohorts, the environment is provided and configured.

Questions

Who is this course for?

Engineers evaluating or porting to RISC-V who need the privileged architecture and the real state of the ecosystem, not the brochure version. It sits at advanced level within the Processor Architecture track.

What do I need to know already?

Specific prerequisites for this course: C and assembly reading ability; Exposure to another ISA's privileged architecture (x86-64 or Arm64); Linux systems programming experience. We confirm levels before the cohort starts and adapt if a group is stronger or weaker than expected.

Can this run privately for my team?

Yes. Any course runs on-site at your offices anywhere, or live online for a distributed team, with labs adapted to your hardware and codebase.

What is the difference between in-person and online?

In person is 3 full days with hardware on your desk, capped at 14. Online is 6 half-day sessions across about two weeks so you can keep working, capped at 20, with remote lab access.

Do you invoice companies?

Yes. Purchase orders are accepted and invoicing is available in USD, EUR, GBP, SAR and CAD.

Upcoming dates

Dates	Where	Seats	Early bird	Regular
18 Oct – 20 Oct 20263 full days	RiyadhIn person · KAFD Conference Centre	4 of 14	—	SAR 9,000
18 Oct – 20 Oct 20263 full days	Kuwait CityIn person · Al Hamra Tower	9 of 14	—	KWD 740
25 Oct – 27 Oct 20263 full days	MuscatIn person · Knowledge Oasis Muscat	4 of 14	—	OMR 920
1 Nov – 8 Nov 20266 half-days	Gulf bandLive online · 09:00–13:00 GMT+3	14 of 20	—	US$1,750
2 Nov – 4 Nov 20263 full days	OttawaIn person · Kanata North Tech Park	9 of 14	—	CAD 3,260
2 Nov – 4 Nov 20263 full days	TorontoIn person · MaRS Discovery District	4 of 14	—	CAD 3,260
2 Nov – 9 Nov 20266 half-days	Europe bandLive online · 09:00–13:00 CET	3 of 20	—	US$1,750
9 Nov – 11 Nov 20263 full days	LondonIn person · Shoreditch Works	9 of 14	GBP 1,680until 10 Oct	~~GBP 1,870~~
9 Nov – 16 Nov 20266 half-days	Americas bandLive online · 13:00–17:00 ET	8 of 20	US$1,580until 10 Oct	~~US$1,750~~
16 Nov – 18 Nov 20263 full days	BerlinIn person · Factory Görlitzer Park	4 of 14	EUR 1,990until 17 Oct	~~EUR 2,210~~

Dates shown for the next few months. If nothing fits, tell us where and when — cohorts are added on demand, and private delivery can be scheduled any week.

More in Processor Architecture

ARC-1013 days CPU Pipelines & Microarchitecture How a modern out-of-order core fetches, schedules and retires instructions, and why that determines the performance ceiling of your code. Foundation Practitioner-taught SAR 6,750Next 18 Oct

ARC-1023 days Cache & Memory Hierarchy The cache hierarchy from L1 to main memory, and the access patterns that decide whether your workload is fast or memory-bound. Foundation Practitioner-taught SAR 6,750Next 18 Oct

ARC-1102 days SIMD & Vector Processing Data-parallel execution on CPUs: AVX-512, NEON and SVE, and how to get the compiler to actually use them. Practitioner Practitioner-taught SAR 5,250Next 15 Nov

ARC-2012 days NUMA & Multi-Socket Systems Non-uniform memory access, node topology discovery, and the placement decisions that quietly cost you throughput. Practitioner Practitioner-taught SAR 5,250Next 8 Nov

ARC-2103 days PCIe & System Interconnects The fabric between CPU, memory and devices: PCIe generations, topology, and the bandwidth you actually get. Practitioner Practitioner-taught SAR 7,880Next 25 Oct

ARC-3014 days x86-64 Systems Programming The x86-64 architecture from a systems perspective: privilege levels, paging, and the mechanisms the kernel is built on. Advanced Practitioner-taught SAR 12,000Next 11 Oct

ARC-3024 days Arm64 Systems Programming AArch64 for systems engineers: exception levels, translation regimes and the memory model that trips up x86 developers. Advanced Practitioner-taught SAR 12,000Next 18 Oct