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FPG-101 · FPGA & Acceleration

FPGA Design for Software Engineers

The mental shift from sequential code to concurrent hardware, taught for people with a software background.

Foundation 4 days in person8 half-days online Max 14 in person

Who this course is for

Software engineers who need to build or evaluate FPGA logic and keep thinking in sequential code — this course rewires that instinct with hardware that runs, not slides.

Prerequisites

Comfortable programming in a compiled language (C/C++ typical)Linux command line for the toolchainBasic digital logic exposure helpful but not assumed — we rebuild it from gatesNo prior HDL experience required

Course outline

Day 1 — From instructions to fabric

  • Why an FPGA is not a fast CPU: concurrency as the default
  • FPGA fabric: LUTs, flip-flops, BRAM, DSP slices and the routing between them
  • Combinational vs sequential logic; what a clock actually disciplines
  • Clock domains and why crossing one is a design decision, not a detail
  • A first look at the Zynq UltraScale+ architecture on the ZCU104

Day 2 — HDL for software readers

  • Modules, ports and wires: structure, not statements
  • always blocks, blocking vs non-blocking assignment, and the latches they hide
  • Verilog or VHDL: read both, write one
  • FSMs and datapaths: the two shapes of digital design
  • Ready-valid handshakes as the function-call convention of hardware

Day 3 — Simulation and verification thinking

  • Testbenches: stimulus, checking, timeouts
  • Self-checking testbenches against a software reference model
  • Waveform debugging: reading what the simulator is actually telling you
  • Assertions, and the bugs that only appear under backpressure and reset
  • Synthesizable vs simulation-only constructs

Day 4 — Synthesis to bitstream

  • Synthesis: what the tool really does to your RTL
  • Place and route; constraints as input, not afterthought
  • Reading utilization and timing reports without panic
  • Programming the ZCU104: bitstream generation and board bring-up
  • The Integrated Logic Analyzer: a scope inside the chip for when simulation lied

Hands-on labs

Labs follow the academy model — 35% principles, 20% guided investigation, 45% engineering studio. Every claim you make in a lab is backed by a trace, a counter or a measurement you captured yourself. How we teach

  1. Lab: Implement a small FSM-plus-datapath block (a UART receiver or pulse counter) in Verilog from a written cycle schedule
  2. Lab: Write a self-checking testbench comparing your RTL against a C or Python reference model with randomized stimulus
  3. Lab: Diagnose an injected latch and a blocking-assignment bug from simulation waveforms alone
  4. Lab: Synthesize and place the design in Vivado; read the utilization and timing reports and justify every warning you keep
  5. Lab: Program the ZCU104 and capture live internal signals with an ILA core; reconcile them with the simulation

Capstone project

Take a byte-oriented algorithm written in C (a CRC or moving-average filter) all the way to hardware: write the cycle-accurate interface contract first, implement the RTL, verify it against the C reference with a self-checking testbench that abuses reset and backpressure, then synthesize for the ZCU104 and demonstrate it on the board with an ILA capture. You keep the RTL, testbench, reports and the evidence that simulation and hardware agree.

What you leave with

  • A working translation from sequential code to concurrent hardware
  • Readable, writable Verilog: FSMs, datapaths and ready-valid interfaces
  • Self-checking testbench habits anchored to a software reference model
  • A complete Vivado run you drove yourself, RTL to bitstream on the ZCU104
  • Report-reading judgment: what to worry about and what to ignore

How it runs

Every course follows the same model: 35% principles, 20% guided investigation, 45% engineering studio. You leave with working code, raw measurements and an evidence-based report — not a certificate of attendance. Read the methodology or see a full sample lesson.

Material is adapted to your kernel version, hardware and workload before a private delivery. For public cohorts, the environment is provided and configured.

Questions

Who is this course for?

Software engineers who need to build or evaluate FPGA logic and keep thinking in sequential code — this course rewires that instinct with hardware that runs, not slides. It sits at foundation level within the FPGA & Acceleration track.

What do I need to know already?

Specific prerequisites for this course: Comfortable programming in a compiled language (C/C++ typical); Linux command line for the toolchain; Basic digital logic exposure helpful but not assumed — we rebuild it from gates; No prior HDL experience required. We confirm levels before the cohort starts and adapt if a group is stronger or weaker than expected.

Can this run privately for my team?

Yes. Any course runs on-site at your offices anywhere, or live online for a distributed team, with labs adapted to your hardware and codebase.

What is the difference between in-person and online?

In person is 4 full days with hardware on your desk, capped at 14. Online is 8 half-day sessions across about two weeks so you can keep working, capped at 20, with remote lab access.

Do you invoice companies?

Yes. Purchase orders are accepted and invoicing is available in USD, EUR, GBP, SAR and CAD.

Upcoming dates

DatesWhereSeatsEarly birdRegular
1 Nov – 4 Nov 20264 full days RiyadhIn person · KAFD Conference Centre 5 of 14 —SAR 9,000
1 Nov – 4 Nov 20264 full days Kuwait CityIn person · Al Hamra Tower 10 of 14 —KWD 740
8 Nov – 11 Nov 20264 full days MuscatIn person · Knowledge Oasis Muscat 5 of 14 OMR 830until 9 OctOMR 920
15 Nov – 24 Nov 20268 half-days Gulf bandLive online · 09:00–13:00 GMT+3 5 of 20 US$1,580until 16 OctUS$1,750
16 Nov – 19 Nov 20264 full days OttawaIn person · Kanata North Tech Park 10 of 14 CAD 2,930until 17 OctCAD 3,260
16 Nov – 19 Nov 20264 full days TorontoIn person · MaRS Discovery District 5 of 14 CAD 2,930until 17 OctCAD 3,260
16 Nov – 25 Nov 20268 half-days Europe bandLive online · 09:00–13:00 CET 10 of 20 US$1,580until 17 OctUS$1,750
23 Nov – 26 Nov 20264 full days LondonIn person · Shoreditch Works 10 of 14 GBP 1,680until 24 OctGBP 1,870
23 Nov – 2 Dec 20268 half-days Americas bandLive online · 13:00–17:00 ET 15 of 20 US$1,580until 24 OctUS$1,750
30 Nov – 3 Dec 20264 full days BerlinIn person · Factory Görlitzer Park 5 of 14 EUR 1,990until 31 OctEUR 2,210

Dates shown for the next few months. If nothing fits, tell us where and when — cohorts are added on demand, and private delivery can be scheduled any week.

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