Train your team

FPG-201 · FPGA & Acceleration

Linux Drivers for FPGA Accelerators

Making an accelerator usable from Linux: memory mapping, DMA, interrupts and a sane userspace interface.

Advanced 3 days in person6 half-days online Max 14 in person

Who this course is for

Engineers productizing FPGA accelerators under Linux — responsible for the kernel driver and the userspace contract that makes programmable logic usable by an application team.

Prerequisites

Linux kernel module basics: a character driver you have written yourselfC programming and comfort reading kernel sourceBasic FPGA/AXI familiarity; labs run on the ZCU104

Course outline

Day 1 — Registers and the user boundary

  • The Zynq PS-PL boundary: what the A53 actually sees of your fabric
  • Register maps and MMIO: ioremap, readl/writel and the barriers between
  • Device tree for PL peripherals: compatible, reg, interrupts, clocks
  • AXI4-Lite as the control plane, and what a bad register map costs
  • Exposing control: ioctl vs sysfs vs mmap, and what each promises

Day 2 — DMA and data movement

  • DMA design for accelerator data movement: coherent vs streaming buffers
  • Ownership transitions and the cache maintenance that prevents stale data
  • The dmaengine API; AXI DMA and scatter-gather operation
  • Zero-copy buffer strategies: dma-buf and contiguous carve-outs
  • Backpressure and flow control between producer logic and consumer software

Day 3 — Interrupts, reconfiguration and the API

  • Interrupt handling: request_irq, threaded IRQs and completion signalling to userspace
  • Signalling patterns that scale beyond one interrupt
  • The FPGA manager framework: loading bitstreams from Linux
  • Partial reconfiguration: when it pays and what the driver must coordinate
  • Designing an API your application team will accept: versioning, error reporting, recovery

Hands-on labs

Labs follow the academy model — 35% principles, 20% guided investigation, 45% engineering studio. Every claim you make in a lab is backed by a trace, a counter or a measurement you captured yourself. How we teach

  1. Lab: Bring up a device-tree-described AXI-Lite peripheral; map its registers and verify reads and writes from a kernel driver
  2. Lab: Implement a DMA transfer path with correct cache ownership — then reproduce a stale-data bug by getting the barriers wrong
  3. Lab: Wire an interrupt from the PL to a threaded IRQ handler and signal a userspace waiter; measure the latency path
  4. Lab: Load a bitstream through the FPGA manager framework and handle the failure modes cleanly
  5. Lab: Critique a supplied accelerator userspace API and produce a better versioned design your application team would sign

Capstone project

Given a working PL accelerator block on the ZCU104 with a register map and a streaming interface, deliver the Linux side end to end: a device-tree binding, a kernel driver with MMIO control, DMA data movement with provable cache correctness, interrupt-driven completion, and a documented userspace API — demonstrated by an application streaming data at a measured sustained rate with an integrity check on every buffer.

What you leave with

  • A working MMIO + DMA + IRQ driver pattern for FPGA accelerators
  • Cache-ownership discipline: why stale DMA data happens and how to prove it cannot
  • FPGA manager and partial-reconfiguration mechanics from Linux
  • Device-tree binding habits for PL peripherals
  • A userspace API design checklist an application team will actually accept

How it runs

Every course follows the same model: 35% principles, 20% guided investigation, 45% engineering studio. You leave with working code, raw measurements and an evidence-based report — not a certificate of attendance. Read the methodology or see a full sample lesson.

Material is adapted to your kernel version, hardware and workload before a private delivery. For public cohorts, the environment is provided and configured.

Questions

Who is this course for?

Engineers productizing FPGA accelerators under Linux — responsible for the kernel driver and the userspace contract that makes programmable logic usable by an application team. It sits at advanced level within the FPGA & Acceleration track.

What do I need to know already?

Specific prerequisites for this course: Linux kernel module basics: a character driver you have written yourself; C programming and comfort reading kernel source; Basic FPGA/AXI familiarity; labs run on the ZCU104. We confirm levels before the cohort starts and adapt if a group is stronger or weaker than expected.

Can this run privately for my team?

Yes. Any course runs on-site at your offices anywhere, or live online for a distributed team, with labs adapted to your hardware and codebase.

What is the difference between in-person and online?

In person is 3 full days with hardware on your desk, capped at 14. Online is 6 half-day sessions across about two weeks so you can keep working, capped at 20, with remote lab access.

Do you invoice companies?

Yes. Purchase orders are accepted and invoicing is available in USD, EUR, GBP, SAR and CAD.

Upcoming dates

DatesWhereSeatsEarly birdRegular
22 Nov – 24 Nov 20263 full days RiyadhIn person · KAFD Conference Centre 6 of 14 SAR 8,100until 23 OctSAR 9,000
22 Nov – 24 Nov 20263 full days Kuwait CityIn person · Al Hamra Tower 11 of 14 KWD 670until 23 OctKWD 740
29 Nov – 1 Dec 20263 full days MuscatIn person · Knowledge Oasis Muscat 6 of 14 OMR 830until 30 OctOMR 920
6 Dec – 13 Dec 20266 half-days Gulf bandLive online · 09:00–13:00 GMT+3 6 of 20 US$1,580until 6 NovUS$1,750
7 Dec – 9 Dec 20263 full days OttawaIn person · Kanata North Tech Park 11 of 14 CAD 2,930until 7 NovCAD 3,260
7 Dec – 9 Dec 20263 full days TorontoIn person · MaRS Discovery District 6 of 14 CAD 2,930until 7 NovCAD 3,260
7 Dec – 14 Dec 20266 half-days Europe bandLive online · 09:00–13:00 CET 11 of 20 US$1,580until 7 NovUS$1,750
14 Dec – 16 Dec 20263 full days LondonIn person · Shoreditch Works 11 of 14 GBP 1,680until 14 NovGBP 1,870
14 Dec – 21 Dec 20266 half-days Americas bandLive online · 13:00–17:00 ET 16 of 20 US$1,580until 14 NovUS$1,750
21 Dec – 23 Dec 20263 full days BerlinIn person · Factory Görlitzer Park 6 of 14 EUR 1,990until 21 NovEUR 2,210

Dates shown for the next few months. If nothing fits, tell us where and when — cohorts are added on demand, and private delivery can be scheduled any week.

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