Vivado Timing Closure & STA

Static timing analysis and the practical work of closing timing on a design that does not meet it.

Practitioner 3 days in person6 half-days online Max 14 in person

Who this course is for

FPGA designers whose designs simulate fine but fail timing on the board — and who are done fixing timing by superstition instead of analysis.

Prerequisites

FPG-101 or equivalent: you can write and synthesize RTLWorking Vivado project experienceLabs run on the ZCU104 (Zynq UltraScale+)

Course outline

Day 1 — What static timing analysis actually checks

Setup and hold from the flip-flop's point of view
Slack, WNS/TNS, and what 'timing met' does and does not mean
Clock skew, uncertainty and jitter as budget line items
Writing correct XDC: create_clock, generated clocks, input/output delays
Reading a timing report: finding the real critical path among thousands

Day 2 — Closing timing on the logic

Pipelining: where to cut a path and what the latency costs
Retiming: letting the tool move registers, and when it cannot
Fanout, placement and routing congestion as physical causes
phys_opt_design and physical optimisation: what it can and cannot fix
Rewriting the RTL the synthesizer keeps misunderstanding

Day 3 — Clock domain crossing and honest constraints

CDC structures: two-flop synchronizers, mux synchronizers, asynchronous FIFOs
The bugs CDC hides: reconvergence, glitches, bit skew on buses
set_false_path and set_multicycle_path as precise exceptions, not violation-hiding
report_cdc and constraint audit as a review practice
Proving functional equivalence survived your timing fixes

Hands-on labs

Labs follow the academy model — 35% principles, 20% guided investigation, 45% engineering studio. Every claim you make in a lab is backed by a trace, a counter or a measurement you captured yourself. How we teach

Lab: Read the failing timing paths on a supplied design and classify each by cause — logic depth, fanout, placement — before changing anything
Lab: Repair a failing path by pipelining and RTL restructuring; verify the fix in the report delta, not by hope
Lab: Write XDC for a multi-clock design from scratch, then audit a bad constraints file and show what each lazy exception hides
Lab: Run report_cdc, fix the real crossings with proper synchronizers, and justify every remaining waiver in writing
Lab: Close timing to positive slack at the target clock and prove functional equivalence with the regression vectors

Capstone project

Given a ZCU104 design that fails timing at a stated target clock (a 288 MHz-class closure exercise), produce a change-by-change closure log: baseline WNS/TNS, a diagnosis per failing path, each fix with its report delta, a constraint audit showing every exception is honest, and final regression evidence that function did not move while slack did.

What you leave with

Fluent timing-report reading: from WNS to the specific path and its physical cause
A correct XDC method, including generated clocks and I/O timing
CDC structures you can defend, with report_cdc as a review gate
Pipelining, retiming and physical-optimisation judgment: which lever for which failure
A closure-log template that makes timing work reviewable by others

How it runs

Every course follows the same model: 35% principles, 20% guided investigation, 45% engineering studio. You leave with working code, raw measurements and an evidence-based report — not a certificate of attendance. Read the methodology or see a full sample lesson.

Material is adapted to your kernel version, hardware and workload before a private delivery. For public cohorts, the environment is provided and configured.

Questions

Who is this course for?

FPGA designers whose designs simulate fine but fail timing on the board — and who are done fixing timing by superstition instead of analysis. It sits at practitioner level within the FPGA & Acceleration track.

What do I need to know already?

Specific prerequisites for this course: FPG-101 or equivalent: you can write and synthesize RTL; Working Vivado project experience; Labs run on the ZCU104 (Zynq UltraScale+). We confirm levels before the cohort starts and adapt if a group is stronger or weaker than expected.

Can this run privately for my team?

Yes. Any course runs on-site at your offices anywhere, or live online for a distributed team, with labs adapted to your hardware and codebase.

What is the difference between in-person and online?

In person is 3 full days with hardware on your desk, capped at 14. Online is 6 half-day sessions across about two weeks so you can keep working, capped at 20, with remote lab access.

Do you invoice companies?

Yes. Purchase orders are accepted and invoicing is available in USD, EUR, GBP, SAR and CAD.

Upcoming dates

Dates	Where	Seats	Early bird	Regular
11 Oct – 13 Oct 20263 full days	RiyadhIn person · KAFD Conference Centre	5 of 14	—	SAR 7,880
18 Oct – 20 Oct 20263 full days	Kuwait CityIn person · Al Hamra Tower	10 of 14	—	KWD 650
25 Oct – 27 Oct 20263 full days	MuscatIn person · Knowledge Oasis Muscat	5 of 14	—	OMR 810
25 Oct – 1 Nov 20266 half-days	Gulf bandLive online · 09:00–13:00 GMT+3	3 of 20	—	US$1,500
26 Oct – 28 Oct 20263 full days	OttawaIn person · Kanata North Tech Park	10 of 14	—	CAD 2,860
2 Nov – 4 Nov 20263 full days	TorontoIn person · MaRS Discovery District	5 of 14	—	CAD 2,860
2 Nov – 9 Nov 20266 half-days	Europe bandLive online · 09:00–13:00 CET	8 of 20	—	US$1,500
2 Nov – 9 Nov 20266 half-days	Americas bandLive online · 13:00–17:00 ET	13 of 20	—	US$1,500
9 Nov – 11 Nov 20263 full days	LondonIn person · Shoreditch Works	10 of 14	GBP 1,480until 10 Oct	~~GBP 1,640~~
9 Nov – 11 Nov 20263 full days	BerlinIn person · Factory Görlitzer Park	5 of 14	EUR 1,740until 10 Oct	~~EUR 1,930~~

Dates shown for the next few months. If nothing fits, tell us where and when — cohorts are added on demand, and private delivery can be scheduled any week.

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