FPG-210 · FPGA & Acceleration
DSP on FPGA: NCO, CIC & FIR
The signal processing building blocks implemented in hardware, with real fixed-point analysis.
Who this course is for
Engineers implementing signal processing in FPGA fabric — SDR, instrumentation or control — who need the standard blocks built right, with the fixed-point analysis to prove it.
Prerequisites
Course outline
Day 1 — Fixed point and oscillators
- Q formats, scaling, saturation and rounding: choosing word lengths deliberately
- Quantisation noise and how error propagates through arithmetic
- Numerically controlled oscillators: phase accumulators and LUT-based sine generation
- Phase truncation, spurs, and what they cost in spectral purity
- Mapping arithmetic onto DSP slices efficiently
Day 2 — CIC and FIR filters
- CIC filters: integrator/comb structure, decimation and the register-growth math
- Droop compensation, and when a CIC alone is enough
- FIR design: coefficients, symmetry exploitation, transposed vs direct forms
- Resource sharing and folding for sample-rate vs clock-rate headroom
- Polyphase decomposition for decimation and interpolation
Day 3 — Architectures and proof
- Digital down-conversion: NCO, mixer, CIC/FIR chain as one architecture
- Lock-in detection: phase-sensitive detection in fixed point
- Golden-model verification: bit-true comparison against a floating reference
- Overflow analysis and worst-case bounds, stated and tested
- Timing and resource closure on the complete chain
Hands-on labs
Labs follow the academy model — 35% principles, 20% guided investigation, 45% engineering studio. Every claim you make in a lab is backed by a trace, a counter or a measurement you captured yourself. How we teach
- Lab: Implement an NCO with a phase accumulator and LUT; measure its output spectrum and identify the spur sources
- Lab: Build a CIC decimator, observe the droop, add a compensation filter, and verify register growth matches your analysis
- Lab: Implement a symmetric FIR exploiting coefficient symmetry and compare resource use against the naive direct form
- Lab: Quantize a floating filter design to fixed point; produce error histograms against golden vectors and set word lengths from a stated budget
- Lab: Assemble a full DDC chain (NCO, mixer, CIC, FIR) and verify it bit-true against the reference model
Capstone project
Build a complete digital down-conversion and lock-in detection chain in RTL — NCO, mixer, CIC decimator, compensating FIR — with a fixed-point design document at its core: Q-format choices with range and error budgets, golden-model test vectors, a stated worst-case overflow analysis, bit-true RTL verification results, and synthesis, timing and resource reports from the ZCU104 target.
What you leave with
- Production NCO, CIC and FIR blocks you built and can defend numerically
- A fixed-point design method: Q formats, error budgets, overflow bounds
- Golden-model verification habits: every numerical claim tied to vectors
- DSP-slice mapping and symmetry/resource-sharing trade-off judgment
- A DDC and lock-in architecture template for SDR and instrumentation work
How it runs
Every course follows the same model: 35% principles, 20% guided investigation, 45% engineering studio. You leave with working code, raw measurements and an evidence-based report — not a certificate of attendance. Read the methodology or see a full sample lesson.
Material is adapted to your kernel version, hardware and workload before a private delivery. For public cohorts, the environment is provided and configured.
Questions
Who is this course for?
Engineers implementing signal processing in FPGA fabric — SDR, instrumentation or control — who need the standard blocks built right, with the fixed-point analysis to prove it. It sits at advanced level within the FPGA & Acceleration track.
What do I need to know already?
Specific prerequisites for this course: FPG-101 or equivalent RTL skills; FPG-110 helpful; Basic DSP: sampling, filtering, frequency response; Comfort with binary arithmetic — we build fixed-point rigor on top. We confirm levels before the cohort starts and adapt if a group is stronger or weaker than expected.
Can this run privately for my team?
Yes. Any course runs on-site at your offices anywhere, or live online for a distributed team, with labs adapted to your hardware and codebase.
What is the difference between in-person and online?
In person is 3 full days with hardware on your desk, capped at 14. Online is 6 half-day sessions across about two weeks so you can keep working, capped at 20, with remote lab access.
Do you invoice companies?
Yes. Purchase orders are accepted and invoicing is available in USD, EUR, GBP, SAR and CAD.
Upcoming dates
| Dates | Where | Seats | Early bird | Regular | |
|---|---|---|---|---|---|
| 1 Nov – 3 Nov 20263 full days | RiyadhIn person · KAFD Conference Centre | 6 of 14 | — | SAR 9,000 | |
| 8 Nov – 10 Nov 20263 full days | Kuwait CityIn person · Al Hamra Tower | 11 of 14 | KWD 670until 9 Oct | ||
| 15 Nov – 17 Nov 20263 full days | MuscatIn person · Knowledge Oasis Muscat | 6 of 14 | OMR 830until 16 Oct | ||
| 15 Nov – 22 Nov 20266 half-days | Gulf bandLive online · 09:00–13:00 GMT+3 | 4 of 20 | US$1,580until 16 Oct | ||
| 16 Nov – 18 Nov 20263 full days | OttawaIn person · Kanata North Tech Park | 11 of 14 | CAD 2,930until 17 Oct | ||
| 23 Nov – 25 Nov 20263 full days | TorontoIn person · MaRS Discovery District | 6 of 14 | CAD 2,930until 24 Oct | ||
| 23 Nov – 30 Nov 20266 half-days | Europe bandLive online · 09:00–13:00 CET | 9 of 20 | US$1,580until 24 Oct | ||
| 23 Nov – 30 Nov 20266 half-days | Americas bandLive online · 13:00–17:00 ET | 14 of 20 | US$1,580until 24 Oct | ||
| 30 Nov – 2 Dec 20263 full days | LondonIn person · Shoreditch Works | 11 of 14 | GBP 1,680until 31 Oct | ||
| 30 Nov – 2 Dec 20263 full days | BerlinIn person · Factory Görlitzer Park | 6 of 14 | EUR 1,990until 31 Oct |
Dates shown for the next few months. If nothing fits, tell us where and when — cohorts are added on demand, and private delivery can be scheduled any week.
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